1/1 
|
Frequency of the wishbone clock
by Unknown on Jan 26, 2009 |
Not available! | ||
|
Hello
I am trying to synthesize the ethmac core for asic using design compiler. I am using 40 MHz both fo MTxClk adn MRxClk. Is there a specification of the frequency of wishbone clk? (wb_clk_i) What is the intended design frequency of this clock or can it operate at any frequency ? Thanks Hakan |
|||
1/1